1. Technical Field
The present invention relates to equalization techniques for high-speed data communications and more particularly to implementations of decision feedback equalizer circuits.
2. Description of the Related Art
As the processing power of digital computing engines grows with improvements in technology, and increasingly interconnected networks are developed to harness this power, higher bandwidth data transmission is needed in systems such as servers and data communication routers. Increasing data line rates above a few gigabits per second becomes challenging, however, due to limited channel bandwidth. The bandwidth of an electrical channel (e.g., transmission line) may be reduced by several physical effects, including skin effect, dielectric loss, and reflections due to impedance discontinuities.
In the time domain, limited channel bandwidth leads to broadening of the transmitted pulses over more than one unit interval (UI), and the received signal suffers from intersymbol interference (ISI). At the data rates being demanded, signal integrity may be significantly degraded even over short distances of interconnect (such as several inches of trace on a circuit board). An effective method of compensating for the signal distortions due to limited channel bandwidth is to add equalization functions to the input/output (I/O) circuitry.
The use of a nonlinear equalizer known as a decision-feedback equalizer (DFE) in the receiver is particularly well-suited to equalizing a high-loss channel. Unlike linear equalizers, the DFE is able to flatten the channel response (and reduce signal distortion) without amplifying noise or crosstalk, which is a critical advantage when channel losses exceed 20-30 dB.
In a DFE, the previously decided bits are fed back with weighted tap coefficients and added to the received input signal. If the magnitudes and polarities of the tap weights are properly adjusted to match the channel characteristics, the ISI from the previous hits in the data stream will be cancelled, and the bits can be detected by a data slicer with a low bit error rate (BER). The adjustment of the tap weights can be performed either manually or automatically by an appropriate adaptive algorithm. A major challenge in the design of a DFE operating at multi-gigabits per second is ensuring that the feedback signals have settled accurately at the slicer input before the next data decision is made.
If a full-rate DFE architecture is used, the feedback loop delay (including the decision-making time of the slicer and analog settling time of the DFE summing amplifiers) needs to be less than one UI. Simply switching to a half-rate architecture does not ease this requirement, as there is still only one UI available to establish the feedback from the previously detected bit, weighted by the first tap coefficient (denoted as h1).
The timing requirements on the first DFE feedback tap can be eased by adopting a technique known as speculation or loop unrolling (See e.g., S. Kasturia and J. H. Winters in “Techniques for High-Speed Implementation of Nonlinear Cancellation”, IEEE J. Sel. Areas Commun., Vol. 9, pp. 711-717, June 1991). In this approach, both +h1 and −h1 are added to the input signal with two parallel summing amplifiers. Since (for binary data transmission) the previous bit can only have two different values, one of these dc offsets added to the input signal represents the correct compensation of the ISI due to the previous bit. The outputs of the two summing amplifiers are then converted by two parallel slicers into two data decisions. Once the previous bit is known, the data decision corresponding to correct polarity of h1 compensation is selected with a 2:1 multiplexer (MUX). Since the h1 compensation is implemented as multiple dc offsets instead of a dynamically changing feedback signal, analog settling time requirements for the first DFE feedback tap are eliminated.
In principle, additional DFE feedback taps (such as the second one, denoted h2, the third one, denoted h3, etc.) may also be implemented by speculation, but the number of parallel data decisions that need to be made grows exponentially with the number of taps. In practice, a more hardware-efficient design of a high-speed DFE can be obtained by adopting a hybrid speculative/dynamic feedback architecture, in which the first tap is implemented by speculation, and the rest of the taps are implemented as dynamically changing feedback signals. With half-rate clocking (or lower rate clocking such as quarter-rate), the critical timing requirement in this hybrid architecture is the loop delay for the h2 feedback tap (including time for analog settling). Since the h2 feedback tap compensates for ISI due to the bit which arrived two UI earlier, ideally there should be 2 UI of time available for accurately establishing the h2 feedback signal at the slicer inputs. This 2 UI loop delay will be referred to here as the “fundamental timing limit” of the hybrid speculative/dynamic feedback DFE.
Unfortunately, this fundamental timing limit cannot be fully achieved in prior art implementations of the hybrid speculative/dynamic feedback DFE. In order not to disturb the h2 dynamic feedback signal prematurely, these implementations deliberately delay the selection between the speculative data decisions until some time after the slicers have sampled the equalized data signals. This delay of the select signal (usually accomplished with a clocked latch) creates a second critical timing path for the DFE. With typical propagation delays, this second critical timing path prevents the DFE from achieving its fundamental timing limit. To allow a DFE to operate at higher frequency and achieve its fundamental timing limit, it is desirable to have an architecture which eliminates this second critical timing path while still preventing disturbance of the h2 feedback signal at the time of data decision by the slicers.